module top(userinput,displaydata,clk,reset,
	   proc0_porta,proc0_porte,proc0_portg,
	   proc1_porta,proc1_porte,proc1_portg,
	   proc2_porta,proc2_porte,proc2_portg);
   /* what's being passed around */
   inout [7:0] proc0_porta /* synthesis altera_chip_pin_lc="@149,@148,@147,@146,@144,@143,@142,@141" */;
   output [3:0] proc0_porte /* synthesis altera_chip_pin_lc="@129,@128,@127,@126" */;
   input [3:0] 	proc0_portg /* synthesis altera_chip_pin_lc="@134,@133,@132,@131" */;

   inout [7:0]  proc1_porta /* synthesis altera_chip_pin_lc="@164,@163,@162,@161,@159,@158,@157,@156" */;
   output [3:0]  proc1_porte /* synthesis altera_chip_pin_lc="@169,@168,@167,@166" */;
   input [3:0] 	 proc1_portg /* synthesis altera_chip_pin_lc="@174,@173,@172,@171" */;

   inout [7:0]  proc2_porta /* synthesis altera_chip_pin_lc="@20,@19,@18,@17,@15,@14,@13,@12" */;
   output [3:0]  proc2_porte /* synthesis altera_chip_pin_lc="@51,@50,@49,@48" */;
   input [3:0] 	 proc2_portg /* synthesis altera_chip_pin_lc="@46,@45,@44,@43" */;

   input 	 clk /* synthesis altera_chip_pin_lc="@91" */;
   input 	 reset /* synthesis altera_chip_pin_lc="@6" */;
   
   reg [31:0]		 count;
   wire [7:0] state_output;


   /* i/o */
   output [7:0] displaydata /* synthesis altera_chip_pin_lc="@111,@110,@118,@117,@116,@115,@114,@113" */;
   reg [7:0] 	displaydata;
   input [7:0] 	userinput /* synthesis altera_chip_pin_lc="@68,@67,@66,@65,@64,@63,@62,@61" */;

   /* stuff */
   router rooter(reset,clk,
		 proc2_portg,proc0_portg,proc1_portg,
		 proc2_porte,proc0_porte,proc1_porte,
		 proc2_porta,proc0_porta,proc1_porta,
                 state_output);

   always @(posedge clk) begin
      count = count + 1;
      case(userinput)
	// bits {1,0}: 00==proc0, 01==proc1, 10==proc2, 11==illegal
	// bit 2: 0==portA, 1=={portG,portE}
	8'b00_00: displaydata <= ~proc0_porta;
	8'b00_01: displaydata <= ~proc1_porta;
	8'b00_10: displaydata <= ~proc2_porta;

	8'b01_00: displaydata <= ~{proc0_portg,proc0_porte};
	8'b01_01: displaydata <= ~{proc1_portg,proc1_porte};
	8'b01_10: displaydata <= ~{proc2_portg,proc2_porte};

	8'b11_00: displaydata <= ~{state_output};
	8'b11_10: displaydata <= ~{state_output};

	default: displaydata <= ~count[25:18];
      endcase // case(userinput)

      if(!reset) displaydata <= ~count[27:20];
   end // always @ (posedge clk)
endmodule // test0